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Digital System Test and Testable Design

Using HDL Models and Architectures

  • Hardback
  • 452 pages
  • Publisher: Springer-Verlag New York Inc.
  • 17.8 x 25.4 x 2.6 cm

£98.54

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This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.
Digital System Test and Testable Design and Sacred And The Profane
Sacred And The ProfaneDigital System Test and Testable Design

  • Title

    Digital System Test and Testable Design

  • Author

    Zainalabedin Navabi

  • Book Format

    Hardback

  • Publisher

    Springer-Verlag New York Inc.

  • Published

    December 2010

  • Edition

    2011 ed.

  • Weight

    1008g

  • Page Count

    452

  • Dimensions

    17.8 x 25.4 x 2.6 cm

  • ISBN

    9781441975478

  • ISBN-10

    1441975470

  • Eden Code

    4639536

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